1. Field of the Invention
The invention relates to a memory device, and more particularly, to a memory device with low power and high density design.
2. Description of the Related Art
For SRAM devices, leakage currents on bit lines affect power consumption and further affect read margins of read operations. In order to decrease leakage currents on bit lines of SRAM devices, the number of memory cells coupled to each one bit line is limited according to the manufacturing processes utilized. For example, 65 nm and 55 nm processes are required to couple 512 memory cells to each one bit line, and 40 nm and 28 nm processes are required to couple 256 memory cells to each one bit line. For 28 nm processes, coupling less memory cells to each one bit line may decrease leakage currents on the bit lines. However, less number of memory cells coupled to each one bit line of an SRAM device will degrade the density of the memory cells in a memory cell array. In this situation, more bit lines are required to obtain the desirable number of memory cells of the SRAM device, and, thus, additional local control circuits and local input/output circuits are also required, which increases area requirements of the SRAM device.